The present invention relates to a circuit and method for receiving data and, in particular, but not exclusively to a circuit and method for receiving data suitable for use in a telecommunications network such as a mobile telecommunications network.
In known arrangements where data is sent from one circuit to another circuit via a data bus, each of the two circuits has its own clock signal. The first clock signal is used by the transmitting circuit to clock the data onto the data bus. The second clock signal is used by the receiving circuit to clock the data from the data bus into, for example, a shift register. These two clock signals may have the same frequency. However, the effective phase difference between the clock signal of the transmitting circuit and the clock signal of the receiving circuit is unknown. This effective phase difference generally depends on two main factors. Firstly, there may be a phase difference between the clock signal of the transmitting circuit and the clock signal of the receiving circuit. Secondly, the transmission delay in the data bus between the transmitting circuit and receiving circuit will contribute to the effective phase difference. As the effective phase difference between the two clock signals of the two circuits is unknown, this can give rise to problems.
Generally, data from the transmitting circuit will be, clocked into the receiving circuit on the rising edge of the clock signal of the receiving circuit. If the data is clocked onto the data bus by the transmitting circuit using a clock signal which has the same frequency as the clock signal used by the receiving circuit, then the clock signal of the receiving circuit will effectively have the same frequency as the incoming data. If the receiving circuit tries to read the incoming data at points where transitions in signal level can occur, then the receiving circuit will be unable to reliably read the data from the transmitting circuit. For example, a xe2x80x9c1xe2x80x9d might be read as a xe2x80x9c0xe2x80x9d or vice versa. This is undesirable.
To deal with this problem, it has been proposed to use a clock signal in the receiving circuit which has twice the frequency of the clock signal used by the transmitting circuit. However, this complicates the circuitry and it is generally preferred that the clock signals of the transmitting circuit and the receiving circuit have the same frequency. It has also been proposed to use a handshaking protocol between the receiving circuit and the transmitting circuit. However, this has the disadvantage that the number of wires between the transmitting circuit and the receiving circuit needs to be increased. In some applications, this is undesirable as it can complicate the arrangement and lead to increased costs.
It is therefore an object of embodiments of the present invention to reduce or at least mitigate these problems.
According to a first aspect of the present invention, there is provided a circuit for receiving data comprising:
a first receiver means having input means for receiving said data and an input for receiving a first clock signal, whereby said data is clocked into said first receiver means by said first clock signal;
a second receiver means having input means for receiving said data and an input for receiving a second clock signal, said first and second clock signals having the same frequency and being phase shifted with respect to one another, whereby said data is clocked into said second receiver means by said second clock signal;
determining means for determining if at least one of said receiver means has correctly received said data; and
means for selectively enabling a first output of one of the receiver means in accordance with the determination made by said determining means.
By using two receiver means which both receive the input data using clock signals having the same frequency but phase shifted with respect to one another, the problems caused by the uncertainty in the effective phase difference between the received data and the clock signal of the receiving circuit can be avoided. In particular, if one receiver means is unable to correctly receive the data due to the effective phase shift between one clock signal and the received data being, for example, substantially zero (or n x 360xc2x0 where n is an integer), the other receiver means should be able to receive the data correctly. It should be appreciated that in certain applications of the present invention, the solution provided is cost effective in that it avoids the need to increase the number of lines between the receiving circuit and a transmitting circuit. The costs and complexity associated with the provision of an additional receiving means may be minimal as compared to the situation where, for example, an additional line is required for a handshaking protocol.
Preferably said received data has half the frequency of the first and second clock signals so that one bit of data will be received in one clock cycle.
Preferably, one of the first and second clock signals is the inverse of the other of said first and second clock signals. This is particularly advantageous in that the two clock signals can be simply obtained using a common clock signal and for example an inverter. However, it should be appreciated that in certain embodiments of the present invention, the first and second clock signals may have a phase shift of other than 180xc2x0.
Preferably, the received data includes a known pattern and the determining means is arranged to determine if the data received by at least one of the receiver means includes said known pattern. This known pattern may be mixed in with the actual data to be transmitted. This provides an easy and simple way to check whether or not the data has been correctly received by the respective receiving circuit.
Preferably, said data includes data indicating the beginning of said data, said determining means being arranged to determine if the data received by at least one of said receiving means includes the data indicating the beginning of the data.
Preferably said determining means is arranged to determine if the data received by at least one receiver includes the known pattern only if the data indicating the beginning of data has been detected.
Preferably, the determining means comprises first comparison means connected to a second output of the first receiver means and second comparison means connected to a second output of the second receiver means. Where the received data includes a known pattern, the respective comparison means may compare the known pattern with the actual pattern received by the respective receiver means.
In one embodiment, the determining means is arranged to determine if one of the first and second receiver means has correctly received the data and said enabling means is arranged to enable the first output of said one of said first and second receiver means if the determining means determines that the data has been correctly received and to enable the first output of the other of said first and second receiving means if the determining means determines that the data has not been correctly received by said one receiver means. In one embodiment of the present invention, the data received by only one of the two receiver means is checked to see if it is correct. If that data is not correct, then the other receiver means may be automatically enabled. This has the advantage that the processing time required in order to determine which receiver means should be enabled can be reduced. It is also a reasonable assumption in certain embodiments of the present invention that if one receiver means has not correctly received the data, the other receiver means has correctly received that data.
In an alternative embodiment of the present invention, the determining means is arranged to determine if the other of the first and second receiver means has correctly received said data only if it is determined by the determining means that said one receiver means has not correctly received said data. It should be appreciated that in certain embodiments of this invention, by also checking to see if the data has been correctly received by the other of the receiver means, a determination can be made as to whether or not the data which is received by the receiving circuit has been corrupted. If neither of the two receiver means correctly receive the data, then it can be assumed that the data has been corrupted.
In a further embodiment of the present invention, said determining means, is arranged to determine if the first and second receiver means correctly receive said data and said enabling means is arranged to enable the first output of one of said receiver means which has correctly received the data. Thus, in this modification, the data received by both the first and second receiver means is checked to see whether or not it is correct. This checking of the received data may occur at the same time for the first and second receiver means.
If data is not correctly received by said first receiver means or by said second receiver means, said enabling means provides an error output. This may provide an indication that the data which has been received by the receiving circuit is corrupted.
Preferably, one of the first and second receiver means is designated as a default receiver means, said enabling means being arranged to enable said default receiver means if both said first and second receiver means have correctly received said data. It should be appreciated that in the embodiment where the data received by only one of said receiver means is checked, the data received by the default receiver means may be checked.
One of the receiver means may be a default receiver and if the default receiver does not correctly receive the data, the other receiver means will be the default receiver.
Preferably, said data is frame data and said default receiver means is the receiver means which was enabled by the enabling means for a previous frame of data. In alternative embodiments of the present invention, a given one of the receiver means may be designated at all times as the default receiver means.
Preferably monitoring means are provided for monitoring the number of times at least one of said receiver means is enabled in a predetermined time period. This provides an indication as to the reliability of the connection between the receiving circuit and a further circuit. If the connection is reliable, then one receiver means should be enabled for the majority if not all of the predetermined time period. However, if the connection is unreliable, then both of the receiver means will be enabled a significant number of times in the predetermined time period.
Preferably said data includes error checking data and said circuit further comprises means for checking the received data for errors.
The clock rate is preferably between 20 and 30 MHz and in one embodiment of the present invention is 26 MHz.
Preferably, embodiments of the invention comprise in combination, a receiving circuit such as described hereinbefore, a transmitting circuit and a data bus between said receiving circuit and said transmitting circuit, said receiving circuit being arranged to receive said data from said transmitting circuit via said data bus. It should be appreciated that when monitoring means are provided, those monitoring means may effectively be monitoring the reliability of the data bus.
The transmitting circuit preferably has a clock signal which is used to clock said data onto said data bus, said clock signal of the transmitting circuit having the same frequency as the first and second clock signals of the receiving circuit. Use of the two receiver means removes the problems of the prior art resulting from the unknown effective phase difference between the transmitting and receiving circuits. It should be appreciated that embodiments of the present invention are also applicable to situations where the frequency of the clock signal of the transmitting circuit is not the same as the clock frequencies of the first and second receiver means.
Preferably, the data is transmitted between the transmitting circuit and the receiving circuit in real time. However in some modifications to the present inventions, buffers may be used to deal with faster data rates. The transmission rate would then not be in real time.
The bus may be a serial bus or a parallel bus. However in some embodiments a serial bus is preferred in that it may be more reliable than a parallel bus. The data is advantageously passed between the circuits in digital form although analogue data may be sent. The use of digital data leads to more reliable results.
Embodiments of the present invention are preferably included in a mobile (cellular) telecommunication network. In particular, it is preferred that embodiments of the present invention be included in the base station of a mobile telecommunication network. For example, embodiments of the invention may be included in the receiving part of a base transceiver station or the transmitting part of a base transceiver station.
Preferably said first circuit is arranged to receive data from a station in said mobile telecommunications network and said second circuit is connected to a digital signal processor of said base transceiver station.
According to a second aspect of the present invention, there is provided a method for receiving data comprising the steps of
clocking said data into a first receiving means using a first clock signal;
clocking said data into a second receiving means using a second clock signal, the first and second clock signals having the same frequency and being phase shifted with respect to one another;
determining if at least one of said receiver means has correctly received said data; and
enabling the output of one of said receiver means in accordance with the determination made in the determining step.